The present invention relates to electronic circuits, and more particularly to a technique for reducing power consumption of a writer head driver circuitry disposed in a data storage media driver.
FIG. 1 is a simplified transistor schematic diagram of a driver circuit 100 used to supply current to a writer head 150 via nodes Hx and Hy. FIG. 2 shows the timing characteristic of the write current Iw so supplied across nodes Hx and Hy. As is seen from FIG. 2, during the boost periods, i.e., (T2−T1) or (T4−T3), current Iw overshoots the steady state current Iwss to provide the required magnetic flux change in the inductor disposed in the write head 150. This current flows, in part, either through transistor pair 102, 108, or 104, 106.
At the end of each boost period, the active transistor pair 102, 108, or 104, 106, is turned off and one of transistor pairs 112, 118, or 114, 116 is turned on so as to start and maintain the steady state operation. FIG. 3 is a timing diagram of a number of signals associated with driver circuit 100.
During the first boost period TB1, voltage signals BSTPL and BSTNL are lowered and voltage signals BSTPR and BSTNR are either raised or are maintained at previously high levels. Accordingly, transistors 102, 108 are turned on and transistors 104, 106 are turned off or maintained off. Therefore, a current path is established from supply voltage VCC to supply voltage VEE via transistors 102, 108, and writer head 150. Boost period TB1 is equal to (T2−T1).
During the second boost period TB2, voltage signals BSTPR and BSTNR are lowered and voltage signals BSTPL and BSTNL are either raised or are maintained at previously high levels. Accordingly, transistors 104, 106 are turned on and transistors 102, 108 are either turned off or maintained off. Therefore, a current path is established from supply voltage VCC to supply voltage VEE via transistors 104, 106, and writer head 150. Steady state transistors 112, 114, 116 and 118 are kept off during the boost periods TB1 and TB2. Boost period TB2 is equal to (T4−T3).
The power consumed by driver circuit 100 during the boost periods is defined by the following expression:
                              (                                    V              CC                        -                          V              EE                                )                ⁢                  (                                                    I                wpr                            ×                              T                B                                                                    T                B                            +                              T                s                                              )                                    (        1        )            where TB represents the boost duration and TS represents the steady state duration.
Positive voltage VP is generated from positive supply voltage VCC. Similarly, negative voltage VN is generated from negative supply voltage VEE. Therefore, the power consumed by driver circuit 100 during the steady state periods is defined by the following expression:
                              (                                    V              CC                        -                          V              EE                                )                ⁢                  (                                                    I                wss                            ×                              T                S                                                                    T                B                            +                              T                S                                              )                                    (        2        )            
As is known, the steady state typically has a much longer duration than the boost period. Consequently, driver circuit 100 has a relatively high power consumption during the steady state periods.